As DRAMs(dynamic random access memory) increase in memory cell density to the 1 Giga level, there is a continuous challenge to maintain sufficiently high storage capacitance despite decreasing cell area. Additionally there is a continuing goal to further decrease cell area. Contact holes of a high integration density device such as DRAMs become inevitably a high aspect ratio, that is, a smaller area comparing with the depth. On the other hand, the capacitance of the capacitor must have more than a constant value despite decreasing cell area. In order to keep a capacitance of such capacitor at an acceptable value, a stacked capacitor or a trench stacked capacitor has been used since it can provide a large capacitor area therein. The stacked capacitor has received much interest in recent years because of the variety of ways that the capacitor can be extended upward over the cell area, increasing its capacitance without requiring additional area on the substrate.
The reduced contact hole size and increased capacitor height bring about undesirably another problems. The conventional method for fabricating a DRAM cell capacitor is depicted in FIG. 1 which illustrates the cross-sectional view of a portion of a semiconductor substrate.
Referring to FIG. 1, a field oxide layer 12 has been formed over the semiconductor substrate 10 so as to define a device area. A gate electrode structure 14 has been formed the device area of the semiconductor substrate 10 disposing a gate oxide layer(not shown) therebetween. Source/drain regions 16 has been formed in and on the device area adjacent to the gate electrode structure 14. An insulating layer 18 has been formed on the gate electrode structure 14 and over the semiconductor substrate 10. An electrically conductive contact plug 20 has been formed in the insulating layer 18 to one of two the source/drain regions 16. A storage node 24 of a capacitor has been formed on the contact plug 20.
The process step for forming the storage node 24 is as follows. After forming the contact plug 20, a polysilicon layer is formed on the contact plug 20 and over the insulating layer 18 to have a thickness of about 10000 .ANG.. A photoresist layer is deposited over the polysilicon layer and then patterned. The polysilicon layer is then etched back using the patterned photoresist layer as a mask, thereby to form the storage node 24. During the step of etching back about 10000 .ANG. thick polysilicon layer, the polysilicon layer at the bottom edge portion of the storage node 24, i.e., the polysilicon layer at the interface between the storage node 24 and the insulating layer 18 is over-etched.
If the storage node 24 is misaligned to the underlaying contact plug 20, the over-etching phenomenon of the polysilicon layer becomes severe as shown in FIG. 1. Accordingly, the storage node falls down in subsequent cleaning process making undesired electrical short between the storage nodes.